1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a plurality of stacked semiconductor chips.
2. Description of the Related Art
To meet demands for a reduction in the size of semiconductor devices, COC (Chip On Chip) techniques are known in which a plurality of semiconductor chips are stacked and mounted on a single semiconductor device (semiconductor package). COC semiconductor devices are disclosed in JP2005-142210A, JP2005-032820A, and JP2007-036184A.
More particularly, such a structure is known in which a plurality of semiconductor chips are stacked in such a way that bump electrodes are disposed on the top and under sides of semiconductor chips and through-vias are used to electrically connect the bump electrodes to circuit elements inside the semiconductor chips. According to this structure, semiconductor devices with a higher integration degree can be implemented, as compared with conventional COC semiconductor devices in which semiconductor chips are electrically connected through bonding wires.
Furthermore, for techniques related to the present invention, a film deposition method using supercritical technology is known, which is disclosed in WO2006105466.
Generally, a resin material referred to as an under-fill material is filled in the spaces between a plurality of stacked semiconductor chips. Conventionally, in the case in which semiconductor chips in a BGA (Ball Grid Array) structure are stacked and filled with an under-fill material, a so-called sidefill process is performed in which a liquid under-fill material is discharged onto the side surfaces of the semiconductor chips and the under-fill material is caused to flow between the semiconductor chips using capillary action produced in the spaces between the semiconductor chips. In this process, the under-fill material is caused to flow between the semiconductor chips, and then the under-fill material is heated and cured.
FIGS. 1A to 1D schematically show a method of filling an under-fill material, which is related to the present invention. As shown in FIG. 1A, semiconductor chip 52 is placed on board 51. Even in the case of using another semiconductor chip (not shown) instead of board 51, and stacking semiconductor chip 52 on this semiconductor chip, the method is similarly performed. The bonding parts of board 51 are electrically connected to the connecting terminals of semiconductor chip 52 through bump electrodes 53 of semiconductor chip 52.
Subsequently, as shown in FIG. 1B, liquid under-fill material 54 is dropped onto and attached to the side surfaces of semiconductor chip 52 placed on board 51. As shown in FIG. 1C, under-fill material 54 flows into the space between board 51 and semiconductor chip 52 because of capillary action produced in the space between board 51 and semiconductor chip 52. Thus, the inside of the space between board 51 and semiconductor chip 52 is filled with under-fill material 54.
Subsequently, as shown in FIG. 1D, board 51 and semiconductor chip 52 filled with under-fill material 54 are heated to cure under-fill material 54 filled in the space between board 51 and semiconductor chip 52. Consequently, filled part 54a is formed between board 51 and semiconductor chip 52.
As described above, in the case of stacking a plurality of semiconductor chips, which are to be electrically connected using through-vias, the semiconductor chips are formed with micro bump electrodes (micro bumps) having a height of a few tens micrometers.
In the case of stacking three or more semiconductor chips, it is necessary to reduce the height of the overall semiconductor package by also reducing the height of the micro bump as low as possible, in order to implement low-profile semiconductor packages. To this end, in the case of stacking three or more semiconductor chips, the spaces between the semiconductor chips are narrowed as well. As a result, according to the filling method which is related to the present invention, it is difficult to completely fill the under-fill material between the semiconductor chips without producing voids (cavities) therebetween because the under-fill material does not sufficiently flow in the spaces between the semiconductor chips.
In the case in which voids remain between the stacked semiconductor chips, it is likely that the under-fill material cracks when heated and cooled in the semiconductor device manufacturing processes after the stacking process. More specifically, in the filling method in which the under-fill material is caused to flow between the semiconductor chips using the above-mentioned capillary actions, it is difficult to fabricate highly reliable semiconductor devices because the spaces, which are narrowed between the vertically stacked semiconductor chips with the development of high integration, cannot be completely filled.
In addition, the method of filling an under-fill material, which is related to the present invention, has another problem in that an overflow (fillet) of under-fill material 54 is formed on the side surfaces of the semiconductor chip; the overflow laterally flows over in the direction orthogonal to the stacking direction of the semiconductor chip, as indicated by width A shown in FIG. 1D. The width of the overflow increases in the lateral direction of semiconductor chips as the number of semiconductor chips to be stacked increases. Because of this, in the case of stacking a large number of semiconductor chips, it is necessary to design the outside dimensions of the semiconductor package to include the overflow width. Therefore, the overflow width is a factor that hampers a reduction in the size of the overall semiconductor device.
JP2007-036184A proposes a method of controlling the overflow width by stacking a plurality of types of semiconductor chips having different outside dimensions. However, the method proposed in JP2007-036184β is not applicable to the case of stacking a plurality of semiconductor chips having the same outside dimensions.